1. Field of the Invention
The present invention relates to a receiving device, a receiving method, and a program. More particularly, the present invention is concerned with a receiving device in which when a noise is contained in a received signal, phase locking processing can be protected, a receiving method, and a program.
2. Description of the Related Art
FIG. 1 is a block diagram showing an example of the constitution of a digital broadcast receiver in accordance with a related art.
In the digital broadcast receiver shown in FIG. 1, a tuner 2 performs frequency conversion, IQ demodulation, or the like on a radiofrequency (RF) signal received at an antenna 1, and outputs a resultant IQ signal to an analog-to-digital (A/D) conversion circuit 3.
The A/D conversion circuit 3 performs analog-to-digital conversion on the IQ signal fed from the tuner 2, and outputs a digital IQ signal to a synchronization circuit 4.
The synchronization circuit 4 performs synchronization processing such as frequency synchronization processing, clock synchronization processing, or frame synchronization processing on the IQ signal fed from the A/D conversion circuit 3, and outputs a resultant IQ signal representing a symbol.
A phase locked loop (PLL) circuit 5 includes a phase error detector 11, a loop filter 12, a numerically controlled oscillator (NCO) 13, and a phase rotation circuit 14.
In the PLL circuit 5, the phase error detector 11 obtains as a phase error a deviation of a symbol from a ideal point, at which the symbol should originally be located, on the basis of the IQ signal, which represents the symbol and is fed from the synchronization circuit 4, and a signal representing a magnitude of phase rotation and being fed back from the NCO 13.
More particularly, when an IQ signal representing a known symbol is fed from the synchronization circuit 4, the phase error detector 11 uses the IQ signal, which represents the known symbol, to obtain as a phase error a deviation from the ideal point at which the symbol should originally be located. When an IQ signal representing a data symbol is fed from the synchronization circuit 4, the phase error detector 11 hard decides the IQ signal representing the data symbol, and obtains the phase error on the basis of the result of hard decision and the IQ signal that has not undergone the hard detection.
The phase error detector 11 uses the obtained phase error and a signal, which represents a magnitude of phase rotation and is fed back from the NCO 13, to obtain a phase error that will be observed even after the phase error has been corrected by the phase rotation circuit 14. The phase error obtained by the phase error detector 11 is fed to a loop filter 12.
The loop filter 12 includes an amplifier 21, an amplifier 22, an arithmetic element 23, a register 24, and an arithmetic element 25. The loop filter 12 filters a phase error fed from the phase error detector 11, and controls the NCO 13, which will be described later, according to the result of the filtering.
More particularly, in the loop filter 12, a phase error is multiplied by loop gains G1 and G2 by the amplifiers 21 and 22 respectively. The resultant value is cumulated by the arithmetic element 23 and register 24. The sum of the output value of the register 24 and a value obtained by multiplying the phase error by the loop gain G1 alone is outputted as a phase correction value from the arithmetic element 25.
The NCO 13 generates a signal, which has a predetermined phase, according to the phase correction value fed from the loop filter 12, and feeds the signal as a signal, which represents the magnitude of phase rotation with respect to an ideal point of an input symbol on a complex plane, to the phase error detector 11 and the phase rotation circuit 14.
The phase rotation circuit 14 rotates the phases of the IQ signal, which represents a symbol and is fed from the synchronization circuit 4, on the complex plane on the basis of the signal representing the magnitude of phase rotation and being fed from the NCO 13, thus corrects the phase error, and outputs the resultant IQ signal.
An error correction circuit 6 performs error correction processing or the like on the IQ signal sent from the phase rotation circuit 14, and outputs the resultant signal.
A demodulation device that demodulates a signal modulated according to the quadrature phase shift keying (QPSK) technique is described in, for example, patent document 1, that is, JP-A-62-178046.